Mechanisms of the performance enhancement by hetero-gate dielectric in tunnel field-effect transistors
KỶ YẾU HỘI NGHỊ KHOA HỌC THƯỜNG NIÊN TRƯỜNG ĐẠI HỌC ĐÀ LẠT NĂM 2018
MECHANISMS OF THE PERFORMANCE ENHANCEMENT BY
HETERO-GATE DIELECTRIC IN TUNNEL FIELD-EFFECT
TRANSISTORS
Nguyen Dang Chiena, Ngo Thi Muaa, Tran Huu Duya, Chun-Hsing Shihb
aFaculty of Physics, Dalat University, Lam Dong, Vietnam
bDepartment of Electrical Engineering, National Chi Nan University, Nantou 54561, Taiwan
*Corresponding author: Email: chiennd@dlu.edu.vn
Abstract
The hetero-gate dielectric (HGD) structure has recently been demonstrated experimentally
in tunnel field-effect transistors (TFETs) to enhance their electrical performance. In this
paper, we adequately examine the mechanisms that the HGD works to ameliorate the
electrical characteristics of TFETs. A typical bulk p-i-n TFET structure is used to exclude
the uncertain effects of body factors on the role of HGD. It is showed that the subthreshold
swing is improved by the presence of a conduction band well near the source/channel
junction, but the swing improvement is limited by the appearance of the hump effect when
the local potential well approaches the source. By analyzing the roles of dielectric
heterojunctions at source- and channel-sides separately, it is found that the on-current
enhanced by the source-side heterojunction is about 5 times larger than by the channel-side
one. The reason is that the source-side heterojunction directly modulates the on-state tunnel
width, whereas the channel-side heterojunction indirectly affects the on-current through
modulating the subthreshold-state tunnel width. Exactly understanding the mechanisms of
the performance enhancement by HGD is important in studying the optimal design of HGD-
TFETs.
Keywords: Hetero-gate dielectric; high-k gate insulator; band-to-band tunneling; tunnel
field-effect transistor (TFET).
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KỶ YẾU HỘI NGHỊ KHOA HỌC THƯỜNG NIÊN TRƯỜNG ĐẠI HỌC ĐÀ LẠT NĂM 2018
CƠ CHẾ NÂNG CAO ĐẶC TÍNH HOẠT ĐỘNG
NHỜ ĐIỆN MÔI CỰC CỔNG DỊ CHẤT TRONG TRANSISTOR
TRƯỜNG XUYÊN HẦM
Nguyễn Đăng Chiếna*, Ngô Thị Mùaa, Trần Hữu Duya, Chun-Hsing Shihb
a Khoa Vật lý, Trường Đại học Đà Lạt, Lâm Đồng, Việt Nam
bKhoa Kỹ Thuật Điện, Đại học Quốc lập Ký Nam, Nam Đầu, Đài Loan
*Tác giả liên hệ: Email: chiennd@dlu.edu.vn
Tóm tắt
Cấu trúc điện môi cực cổng dị chất (HGD) gần đây đã được chứng minh bằng thực nghiệm
trong các transistor trường xuyên hầm (TFET) để nâng cao đặc tính điện của chúng. Trong
bài báo này, chúng tôi nghiên cứu chi tiết các cơ chế giúp cho điện môi cực cổng dị chất có
thể cải thiện đặc tính điện của TFET. Cấu trúc p-i-n TFET khối đặc trưng được sử dụng để
loại trừ những ảnh hưởng không xác định của các yếu tố thân linh kiện đến vai trò của HGD.
Nghiên cứu chỉ ra rằng độ dốc dưới ngưỡng được cải thiện nhờ sự có mặt của một hố thế
định xứ gần chuyển tiếp nguồn/kênh, nhưng sự cải thiện này bị giới hạn bởi sự xuất hiện của
hiệu ứng bướu khi hố thế này tiến gần tới cực nguồn. Bằng việc phân tích vai trò của các
chuyển tiếp dị chất phía nguồn và kênh một cách riêng rẽ, nghiên cứu chỉ ra rằng dòng mở
được tăng lên nhờ chuyển tiếp dị chất phía nguồn lớn hơn khoảng 5 lần nhờ chuyển tiếp dị
chất phía kênh. Nguyên nhân là do chuyển tiếp dị chất phía nguồn hiệu chỉnh trực tiếp độ
rộng xuyên hầm ở trạng thái mở, trong khi chuyển tiếp dị chất phía kênh chỉ ảnh hưởng gián
tiếp tới dòng mở thông qua hiệu chỉnh độ rộng xuyên hầm ở trạng thái dưới ngưỡng. Việc
hiểu chính xác các cơ chế làm nâng cao đặc tính hoạt động của TFET nhờ cấu trúc HGD là
rất quan trọng trong quá trình thiết kế tối ưu cho các TFET có điện môi cực cổng dị chất.
Từ khóa: Điện môi cực cổng dị chất; chất cách điện có độ điện thẩm cao; xuyên hầm qua
vùng cấm; transistor trường xuyên hầm (TFET).
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KỶ YẾU HỘI NGHỊ KHOA HỌC THƯỜNG NIÊN TRƯỜNG ĐẠI HỌC ĐÀ LẠT NĂM 2018
INTRODUCTION
1.
Traditional metal-oxide-semiconductor field-effect transistors (MOSFETs) have
exhibited the unsuitability for use in ultra-low power applications since they are subjected
to the physical limit of 60 mV/decade subthreshold swing at room temperature
(International Technology Roadmap for Semiconductors, 2015). To overcome this
fundamental limit of MOSFETs, one has proposed tunnel field-effect transistors (TFETs)
whose steep on-off switching with sub-60 mV/decade subthreshold swing has been
experimentally demonstrated (Appenzeller et al., 2004; Choi et al., 2007). Other
significant advantages of TFETs over MOSFETs are small power dissipation (Koswatta
et al., 2009) and high dimensional scalability (Bardon et al., 2010). However, the band-
to-band tunneling, which makes the breakthrough of the kT/q limit, is also responsible for
low on-current in TFETs because the tunneling probability is relatively small (Seabaugh
& Zhang, 2010). Therefore, enhancing on-current has become the most challenge of
TFET devices and attracted much attention since the last 2000s.
In order to enhance the conduction current of TFETs, many methods relating to
both material and structure techniques have been proposed to reduce the tunnel barrier
and/or to increase the tunneling area at on-state (Nayfeh et al., 2009; Kao et al., 2012;
Chien et al., 2013). Since the tunneling probability is exponentially increased with
decreasing the height of tunnel barrier, using low-bandgap materials has been realized as
one of most effective techniques to boost the on-current (Nayfeh et al., 2009). In the other
hand, because of the same dependences of the tunneling probability on the width and the
height of tunnel barrier, narrowing the tunnel barrier has always be concerned largely.
While the tunnel barrier height is basically determined by the material bandgap, there are
so many factors that affect the tunnel barrier width such as source/drain doping profile
(Chien & Shih, 2017), gate insulator and spacer (Choi et al., 2016), gate materials (Noor
et al., 2017), body thickness (Toh et al., 2007), structure of source/channel junction
(Mohata et al., 2011), overall device structure that determines the way of tunneling
motions (Vendenberghe et al., 2008), dimensions of device parameters (Chien & Shih,
2016), supply voltage (Chien et al., 2016), etc. Despite the complexity, the basic principle
of controlling the tunnel width by gate voltage is applied in all cases. Since the gate is
insulated from the channel by a gate insulator, properly designing gate-oxide layer is an
important method to increase the gate control and thus the on-current. The simplest way
to do that is scaling down equivalent-oxide thickness (EOT) by using high-k dielectric
and/or decreasing physical oxide thickness (Boucart & Ionescu, 2007; Chien & Shih,
2017). To further improve the electrical performance of TFETs, both structure and
material techniques have been combined to propose an advanced structure of hetero-gate
dielectric (HGD) which consists of different gate dielectric materials at the source,
channel and drain (Choi et al., 2010; Choi et al., 2016). However, the mechanisms of the
performance enhancement in HGD-TFETs have not been adequately elucidated,
particularly the roles of the local potential well and the source-side heterojunction have
not been clearly understood yet.
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In this paper, the mechanisms that make the subthreshold swing decreased and the
on-current increased are properly elucidated to provide an adequate understanding on the
device physics and design of HGD-TFETs. In order to do so, two-dimensional device
simulations based on the simulator Medici (Synopsys MEDICI User’s Manual, 2010) are
performed to produce the electrical characteristics of TFETs. The paper is organized into
6 main sections, including the first introduction and the last conclusion. After describing
the structure and simulation models in section 2, the ambipolar behavior, subthreshold
swing and on-current improvements are presented in sections 4, 5 and 6, respectively.
2.
DEVICE STRUCTURE AND SIMULATION SETUP
Figure 1 sketches the schematic structure of hetero-gate dielectric TFETs that are
investigated in this study. Generally, there are two low-k/high-k heterojuctions presented
in the gate insulator layer which has a fixed physical thickness of 3 nm. The locations of
source- and channel-side heterojunctions were specified by parameters Xsh and Xch,
respectively. SiO2 with a dielectric constant of 3.9 was typified for the low-k insulator
whereas the permittivity of high-k dielectric was varied and stated clearly in each
investigation. A typical bulk TFET structure based on the point-tunneling was employed
to avoid the impacts of body parameters on the device performance that can make changes
in the major role of HGD. In all TFETs, low-bandgap Ge was used to get high on-currents
for practical significance of the study. Both the source and drain regions were respectively
doped with equally high acceptor and donor concentrations of 1020 cm-3. To exactly
investigate the effects of the heterojunction positions, the ideal abruptness of doping
profiles was assumed at the source and the drain. A small donor concentration of 1017 cm-
3
was specified in the channel which was assigned a long length of 100 nm to exclude
possible short-channel effects which may cause difficulties in studying the effects of
HGD layer on device characteristics. Aluminium with a workfunction of 4.27 eV was
applied at the gate terminal.
Hetero-Gate Dielectric TFET
Drain
Gate
Source
Low-k
High-k
Low-k
p+
1020 cm-3
n+
1020 cm-3
n
1017 cm-3
x
Xsh
0
Xch
Channel-Side Heterojunction
Source-Side Heterojunction
Bulk
Figure 1. Schematic structure of hetero-gate dielectric TFETs used in the study
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Examining the operation, mechanism and design of HGD is based on the electrical
characteristics of TFETs such as current-voltage curves, energy-band diagrams, tunneling
rate contour which are obtained by carrying out the simulations of two-dimensional
devices. The total tunneling current in Ge-based TFETs is contributed by both direct and
indirect tunneling processes. However, if noting that, at comparable bandgaps, the direct
tunneling probability is much greater than the indirect one, the direct tunneling dominates
the on-current of Ge TFETs because the difference between direct and indirect bandgaps
is rather small (0.14 eV) (Kao et al., 2012). In simulations, the direct tunneling rate (Gdir)
is generated by the nonlocal approach of the Kane model to calculate the TFET current
as (Kane, 1961):
Eg3/ 2
2
(1)
Gdir A
exp(B
)
E1g/ 2
10-3
10-5
0.4
0.0
(b)
: EOT = 2 nm
Uniform-Gate Dielectric TFETs
: EOT = 0.5 nm
Channel
10-7
-0.4
-0.8
-1.2
-1.6
10-9
Tunnel Width
Drain
10-11
10-13
10-15
Vgs = 0.1 V
Vds = 0.7 V
Decrease EOT:
3, 2, 1, 0.5, 0.3 nm
Uniform-Gate
Dielectric TFETs
Vds = 0.7 V
0.6
(a)
-0.4
-0.2
0.0
0.2
0.4
0.8
1.0
-60
-40
-20
0
20
40
Distance to Drain (nm)
Gate-to-Source Voltage (V)
Figure 2. (a) Current-voltage characteristics of uniform-gate dielectric TFETs with
various EOTs; (b) Energy-band diagrams at off-state of uniform-gate dielectric
TFETs with different EOTs
where Eg is the bandgap of semiconductor; ξ is the nonlocal electric field; A and B are
material parameters which have been calculated to get 1.6×1020 eV1/2/cm.s.V2 and
9.5×106 V/cm.eV3/2, respectively. The band gap narrowing due to heavy-doping, the
Fermi-Dirac distribution and Shockley-Read-Hall recombination were also included in
simulations.
3.
AMBIPOLAR CURRENT SUPPRESSION
In a typical p-i-n TFET structure, both the source/channel and drain/channel
junctions can play a role of tunnel junction because their tunneling window can be open
up by appropriate gate voltages. Expectedly, the tunneling window at source/channel
junction is largely open up at on-state and completely closed down at off-state to engender
favourable on-off transition. Because of the symmetry between the n- and p-type
operation modes, the ambipolar current always presents in any p-i-n TFETs. Many factors
can affect the ambipolar current, for example, gate-oxide thickness, material bandgap,
gate-drain alignment, drain concentration, length and voltage.
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To observe the effect of EOT on the ambipolar behavior, figure 2(a) shows the
current-voltage curves of TFETs whose gate dielectric layer is uniform for various EOT
values. It is seen that although the on-current is largely enhanced, the ambipolar off-
current is also increased severely with decreasing the EOT. The serious increase of
ambipolar current limits the exploitation of scaling EOT for ameliorating the on-current
of TFETs. To explain the variation trend of ambipolar current, figure 2(b) plots the off-
state energy-band diagrams at the drain-channel junction of TFETs with different EOTs.
The thinner EOT results in the stronger gate control to bend the energy-band diagram at
the drain/channel junction more largely. As a result, the tunnel width is narrowed and thus
the tunneling current is increased with scaling EOT. Although some methods have been
suggested to effectively suppress the ambipolar current, they also lead to considerable
disadvantages. For example, the drain engineering, which includes decreasing the
concentration, increasing the length or gate-drain underlap, causes the on-current
degradation because of the increase in resistance.
10-3
10-5
0.9
0.6
Hetero-Gate Dielectric TFETs
Hetero-Gate
Dielectric TFETs
Source
Xsh = Source Length
Xch = 50 nm
0.3
Xsh = Source Length
Xch = 50 nm
10-7
0.0
Tunnel Width
10-9
EOT of Low-k
Dielectric: 3 nm
Vds = 0.7 V
-0.3
-0.6
-0.9
-1.2
Vgs = 0.8 V
10-11
10-13
10-15
Decrease EOT
of High-k Layer:
3, 2, 1, 0.5, 0.3 nm
High-k Dielectric:
: EOT = 0.5 nm
: EOT = 2 nm
(b)
Channel
Vds = 0.7 V
(a)
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
-20
0
20
40
Distance to Drain (nm)
Gate-to-Source Voltage (V)
Figure 3. (a) Current-voltage curves of HGD-TFETs with single dielectric
heterojunction structure for various EOTs of high-k layers; (b) Energy-band
diagrams at on-state of HGD-TFETs with different EOTs of high-k layers
It is reminded that the on-state tunneling occurs at the source/channel junction
whereas the off-state tunneling generates at the drain/channel junction of TFETs. Because
the purpose of introducing high-k dielectric into TFETs is to shorten the on-state tunnel
path at source/channel junction, replacing the gate insulator layer at drain side by a low-
k dielectric does not change the action of high-k dielectric at source side on the on-current.
This is an important idea from which the HGD has been introduced into TFET devices.
To inspect above reasoning, Figure 3(a) shows the input characteristics of HGD-TFETs
with a single dielectric heterojunction (i.e., corresponding to Xsh = source length, Xch =
half of channel length) for various EOTs of high-k layer. Because the EOT of low-k layer
is fixed, the ambipolar current is remained unchanged at a low level regardless of
decreasing the EOT of high-k layer. In the other hand, the increase of the on-current by
scaling EOT in the single dielectric heterojunction TFETs is completely similar to that in
the uniform-gate dielectric TFETs. As shown in figure 3(b), the on-state energy-band
diagram at the source/channel junction of the HGD-TFET with the thinner EOT is curved
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more strongly than that with the thicker EOT to form the shorter tunnel path and thus
attain the higher on-current.
4.
SUBTHRESHOLD SWING IMPROVEMENT
The advantage of HGD is not only in the ambipolar current but also in the
subthreshold swing if the HGD structure is properly designed (Choi et al., 2010). It has
been demonstrated that the improvement of subthreshold swing in HGD-TFETs is
originated from the formation of a local minimum of conduction band near the
source/channel junction which makes a more abrupt decrease of tunnel width. Choi et al.
(2010) explained that the decrease in the profitability of HGD at small Xch (< 6 nm) is
due to the shallowing of the conduction band well. However, this section will show that
it is not a main reason.
10-3
10-5
1.0
0.8
Hetero-Gate Dielectric TFETs
Hetero-Gate Dielectric TFETs
Position of Right
Heterojunction:
0.6
Source
Xsh = Source Length
Vds = 0.7 V
0.4
10-7
: Xch = 8 nm
: Xch = 4 nm
0.2
10-9
0.0
Tunneling
-0.2
-0.4
-0.6
-0.8
-1.0
10-11
10-13
10-15
Vgs = 0.3 V
Vds = 0.7 V
Channel
Position of Channel-
Side Heterojunction:
Xch = 20, 12, 8, 6, 4, 2 nm
(a)
(b)
Xsh = Source Length
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
-30
-20
-10
0
10
20
30
40
50
Distance to Source (nm)
Gate-to-Source Voltage (V)
Figure 4. (a) Input transfer characteristics of HGD-TFETs with various Xch; (b)
Energy-band diagrams at subthreshold state of HGD-TFETs with different Xch
Figure 4(a) shows the current-voltage characteristics of HGD-TFETs with various
positions of the channel-side heterojunctions (Xch). To exactly investigate the effects of
Xch on the device characteristics, the structure of single dielectric heterojunction (Xsh =
source length) is used to exclude any influences of the second dielectric heterojunction.
When the position of the channel-side heterojunction is far from the source (Xch ≥ 8 nm),
the subthreshold swing decreases along with decreasing the Xch. However, when the Xch
decreases smaller than 8 nm, the overall subthreshold swing starts increasing. Notably,
the subthreshold region is clearly divided into high and low swing regions which are
separated by a hump voltage (Vhump). This hump effect makes the average subthreshold
swing increased. To understand the appearance of the hump effect in short-Xch HGD-
TFETs, figure 4(b) displays the energy-band diagrams at subthreshold state of HGD-
TFETs with Xch = 8 and 4 nm. As seen in the figure, the conduction band well is higher
in the Xch=4nm than in the Xch=8nm TFET. This makes the abrupt change of tunnel width
triggered more lately in the short-Xch than in the long-Xch device. Before the abrupt
decrease of tunnel width occurs (Vgs ≤ Vhump), the tunnel width is small and thus the
tunneling current is high (higher than 0.1 pA/µm) in the Xch=4nm TFET, whereas those
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in the Xch=8nm TFET are respectively large and low (lower than 0.1 pA/µm). This is
because electrons tunnel to the outside of the well if Vgs ≤ Vhump and to the inside of the
well if Vgs > Vhump. As a result, the hump effect is clearly observed in the Xch=4nm TFET.
The shorter the Xch, the more severe the hump effect is. The hump effect, which
deteriorates the subthreshold swing and associated on-current, occurs because the
conduction band well is moved down to low potential region near the source, but not by
the shallowing of the well.
If the on-current is determined at the gate voltage of 0.7 V (= Vdd) higher than the
onset voltage (Vonset), i.e., a constant value of (Vgs – Vonset), a decrease in subthreshold
swing indirectly results in an increase in on-current and vice versa. It is noted that Vonset
is defined as the gate voltage when the drain current is 0.1 pA/µm. Because there are two
opposite variation trends of subthreshold swing when the Xch is decreased, there exits an
optimal Xch to minimize the subthreshold swing and maximize the on-current as shown
by Choi et al. (2010). To evaluate how much the on-current is enhanced and what is the
optimal length of Xch in the p-i-n TFET with a typical bulk structure, Figure 5(a) presents
the on-current as a function of the source-side heterojunction position (Xch). The plot
shows that the on-current is maximized at Xch = 8 nm and 22% greater than that of the
high-k only TFET (compared to 6 nm and 30 %, respectively, as reported by Choi et al.
(2010), but they used the SOI structure and Vdd = 1 V). To explain the decrease of
subthreshold swing with decreasing Xch ( ≥ 8 nm), Figure 5(b) shows the energy-band
diagrams at onset state of the HGD-TFETs with different Xch. Before reaching to the onset
state, the tunnel widths in the two devices are large and the tunneling currents are lower
than the background off-current. When going to the onset state, the tunnel widths are
abruptly decreased. As shown in the figure, however, the tunnel width is shorter, the
abruptness is higher and thus the subthreshold swing is smaller in the Xch=8nm than in
the Xch=20nm TFET.
80
70
60
50
40
30
20
10
0.6
(a)
(b)
Source
Hetero-Gate
Dielectric TFETs
0.4
Vds = 0.7 V
Xsh = Source Length
Xsh = Source Length
0.2
Tunneling Path
Position of Source-
Vgs Vonset = Vds = 0.7 V
0.0
Side Heterojunction:
: Xch = 8 nm
: Xch = 20 nm
Hetero-Gate Dielectric TFETs
Onset State
-10
Channel
30 40
-0.2
-20
0
10
20
30
40
50
0
10
20
Position of Channel-Side Heterojunction (nm)
Distance to Source (nm)
Figure 5. (a) On-current of HGD-TFETs as a function of the position of channel-
side heterojunction (Xch); (b) Energy-band diagrams at onset state of HGD-TFETs
with different Xch
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ON-CURRENT ENHANCEMENT
5.
As shown in previous section, properly designing the position of channel-side
heterojunction (Xch) in HGD-TFETs can ameliorate the device on-current. However, the
on-current enhancement by optimizing Xch is relatively limited because (1) the on-current
is indirectly enhanced through the decrease of subthreshold swing and (2) the channel-
side heterojunction has to be kept far enough from the source/channel junction, where the
on-state tunneling occurs, to avoid the hump effect. It is inferred from this reasoning that
the on-current may be more significantly enhanced by optimally designing the source-
side dielectric heterojunction which is close to the source doping junction.
10-3
140
(b)
Hetero-Gate Dielectric TFETs
Vds = 0.7 V
120
100
80
60
40
20
0
10-5
10-7
Xch = 50 nm
10-9
Position of Source-
Side Heterojunction:
Xch = 50 nm
Circle : Xsh = 0 nm
Triangle : Xsh = 4 nm
Square : Xsh = 4 nm
10-11
10-13
10-15
Vgs Vonset = Vds = 0.7 V
Hetero-Gate Dielectric TFETs
(a)
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
-10
-8
-6
-4
-2
0
2
4
6
Gate-to-Source Voltage (V)
Position of Source-Side Heterojunction (nm)
Figure 6. (a) Current-voltage characteristics of HGD-TFETs with different
positions of source-side heterojunctions (Xsh); (b) On-current of HGD-TFETs as a
function of Xsh
Figure 6(a) depicts the gate transfer characteristics of HGD-TFETs with three
different positions of the source-side heterojunctions. To avoid the uncertain effects of
the channel-side heterojunction position on the device characteristics, the large value of
Xch = 50 nm is fixed in this investigation. It is seen that the position of source-side
heterojunction does not impact the subthreshold swing noticeably, but directly influences
the on-state current of HGD-TFETs. In these three cases, the on-current is highest when
the heterojunction and doping junction are exactly aligned (Xsh = 0) and lower than the
maximum one for two remaining cases (Xsh = 4 and 4 nm). To inspect more details about
the optimization of source-side heterojunction, figure 6(b) shows the on-current of HGD-
TFETs as a function of source-side heterojunction position (Xsh). Interestingly, the on-
current is maximized at Xsh = 1 nm but not 0 nm as normally predicted. Decreasing or
increasing Xsh also results in decreasing the on-current; however, the on-current
degradation is more serious for the positive than for the negative side. On the negative
side, the on-current is saturated when Xsh ≤ 5 nm at the current level that is same as that
of the high-k only TFET. So, by introducing and designing the source-side heterojunction
appropriately, the on-current is significantly enhanced, namely 100% greater that of the
HGD-TFET without source-side dielectric heterojunction.
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KỶ YẾU HỘI NGHỊ KHOA HỌC THƯỜNG NIÊN TRƯỜNG ĐẠI HỌC ĐÀ LẠT NĂM 2018
The rapid degradation of the on-current on the positive side of Xsh is simply
because expanding the low-k dielectric on the channel-side results in weakening the gate
control on the source/channel junction. Therefore, the tunnel width is significantly
increased with lengthening Xsh, as seen in Figure 7(a) in which the on-state energy-band
diagrams of HGD-TFETs with Xsh = 1 and 4 nm are drawn. For the negative side of Xsh,
Choi et al. (2016) has claimed that the decrease of on-current with negatively increasing
the Xsh is attributed solely to the increase in the coupling between the gate and source
regions. The strong coupling reduces the electric field at the source/channel junction, or
equivalently increases the tunnel width as compared in figure 7(a) between the energy-
band diagrams with Xsh = 4 and 1 nm. However, if only looking at the electric field or
the tunnel width, we cannot understand why the on-current of the Xsh=4nm TFET is
higher than that of the Xsh=4nm counterpart whereas the tunnel width is larger in the
Xsh=4nm than in the Xsh=4nm TFET. It suggests that there must be other mechanism
that has not been realized previously to explain for this inconsistency. Figure 7(b) shows
the contours of BTBT generation rates at on-state in the HGD-TFETs with Xsh = 4 and
4 nm. The tunneling area is considerably larger in the Xsh=4nm than in the Xsh=4nm
TFET, which explains properly for the difference in their on-currents. The large tunneling
area in the Xsh=4nm device is due to the lateral extension of the tunneling into the source.
The extended area can only be the line-tunneling, i.e., electrons perform band-to-band
tunneling in the vertical direction. The line-tunneling is triggered because the strong
coupling between the gate and the source bends the source energy-bands largely to open
up a vertical tunneling window. Although the tunneling area is larger, but the tunneling
rate is much smaller, the on-current of the Xsh=4nm TFET is still lower than that of the
Xsh=1nm TFET.
Hetero-Gate Dielectric TFETs
0.9
0.6
(b)
(a)
Xch = 50 nm
Gate
Low-k
High-k
Xsh = -4 nm
Source
Vgs = 0.8 V
Vds = 0.7 V
Position of Source-
Side Heterojunction:
0
0.3
5
: Xsh = - 4 nm
: Xsh = 0 nm
: Xsh = 4 nm
Source
32
30
28
26
24
22
20
18
16
10
15
0.0
Tunnel Width
Xch = 50 nm
Gate
High-k
Xsh = 4 nm
-0.3
-0.6
-0.9
-1.2
Vgs = 0.8 V
Vds = 0.7 V
Low-k
0
5
Channel
Source
Hetero-Gate
Dielectric TFETs
10
15
-20
-15
-10
-5
0
5
10
15
20
-10 -8
-6
-4 -2
0
2
4
6
8
10
Distance to Source (nm)
Distance to Source (nm)
Figure 7. (a) Energy-band diagrams at on-state of HGD-TFETs with different Xsh;
(b) Contours of BTBT generation rates at on-state in HGD-TFETs with different
Xsh
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KỶ YẾU HỘI NGHỊ KHOA HỌC THƯỜNG NIÊN TRƯỜNG ĐẠI HỌC ĐÀ LẠT NĂM 2018
6.
CONCLUSION
By using two-dimensional numerical simulations, the device physics of HGD-
TFETs has been explored to achieve an adequate understanding on the mechanisms of
how the TFET performance is enhanced by the HGD. The suppression of detrimental
hump effect, which emerges in HGD-TFETs with a short high-k layer, is expected to
exploit the benefit of HGD effectively. In addition, the source-side heterojunction has to
be more carefully designed and fabricated because the on-current of HGD-TFETs is more
sensitive on the position of the source- than on the channel-side heterojunction.
ACKNOWLEDGMENTS
This research is funded by the Ministry of Education & Training and Dalat
University, Vietnam. This work is also supported by the National Center for High-
Performance Computing of Taiwan.
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